1. Field of the Invention
The present invention relates to a solid-state imaging device, for example, a threshold voltage modulation system MOS image sensor, and a method for driving the same.
2. Description of the Related Art
An amplification type solid-state imaging device is nowadays widely used as a solid-state imaging device, in which each of unit pixels has a signal amplification function and signals are sequentially read from each unit pixel by a scanning circuit. Such an amplification type solid-state imaging device is available in a planar type and a vertical type. In a planar type amplification type solid-state imaging device, elements including a reset section and a pixel selection section are arranged in a planar manner in each unit pixel. In a vertical type amplification type solid-state imaging device, such elements are arranged vertically.
For example, Japanese Laid-Open Publications Nos. 11-195778 and 2002-134729 propose a vertical type amplification type solid-state imaging device which is called a threshold voltage modulation system MOS image sensor. This image sensor includes a MOS transistor (insulation gate type field effect transistor) for detecting a signal corresponding to an amount of light and a carrier pocket (charge accumulation region) provided below a channel region of the MOS transistor.
A threshold voltage modulation system MOS image sensor (also referred to simply as “MOS image sensor” or “image sensor”) will be described in detail with reference to FIGS. 6A and 6B.
FIGS. 6A and 6B show a part of the threshold voltage modulation system MOS image sensor. FIG. 6A is a top view of a unit pixel section 10, which corresponds to one pixel of the image sensor. FIG. 6B is a cross-sectional view of the unit pixel section 10 taken along line A–A′ in FIG. 6A. The image sensor includes a plurality of unit pixel sections 10.
Referring to FIGS. 6A and 6B, each unit pixel section 10 includes a light receiving diode 11 for performing photo-electric conversion of light incident thereon to generate charges in an amount corresponding to the amount of incident light, and a MOS transistor 12 for detecting a signal corresponding to the amount of incident light. The MOS transistor 12 is adjacent to the light receiving diode 11.
The light receiving diode 11 includes an N-type well region 14 formed in a surface region of a P-type substrate 13, and a P-type well region 15 formed on the N-type well region 14. An area of the P-type well region 15, which is in the light receiving diode 11, acts as a light receiving region and generates charges (holes) when irradiated with light. The P-type well region 15 connects the light receiving diode 11 and the MOS transistor 12 to each other.
The MOS transistor 12 includes an annular gate electrode 16, an N-type source region 17 surrounded by the gate electrode 16, an N-type drain region 18 provided outside the gate electrode 16, an N-type layer 19 acting as a transistor channel region, and a P-type carrier pocket region 20 acting as a charge accumulation region. The P-type carrier pocket region 20 is a p-type hole pocket region in this example.
The gate electrode 16 is provided so as to surround the source region 17. The source region 17 is provided inside the gate electrode 16. The drain region 18 is provided so as to surround the annular gate electrode 16.
The N-type layer 19 is provided right below the gate electrode 16 as a transistor channel region between the source region 17 and the drain region 18.
The carrier pocket region 20 is provided at a position which is in the P-type well region 15, below the gate electrode 16 and the N-type layer 19, and in the vicinity of the source region 17. Horizontally seen (FIG. 6A), the carrier pocket 20 is annular and surrounds the source region 17. Charges generated in the light receiving diode 11 are accumulated in the carrier pocket region 20 through the P-type well region 15. For a signal read operation, a prescribed unit pixel section 10 is selected by a gate voltage applied to the gate electrode 16, and an output signal (imaging signal) representing a voltage value corresponding to the amount of the charges accumulated in the carrier pocket region 20 is output from the source region 17. For a reset operation, the charges accumulated in the carrier pocket region 20 are discharged toward the substrate 13 from the carrier pocket region 20 through the drain region 18 by a gate voltage applied to the gate electrode 16.
The MOS image sensor includes a plurality of unit pixel sections 10 in a matrix, i.e., in rows and columns. Gate voltages of a selected row and gate voltages of an unselected row are separately controlled by a gate driving circuit (not shown), so that image signals for respective selected unit pixel sections 10 are sequentially read through a selected column.
The operation of the MOS image sensor will be described with reference to FIGS. 7 and 8.
FIG. 7 shows a potential distribution of the unit pixel section 10 shown in FIGS. 6A and 6B in operation (during an imaging cycle). In FIG. 7, the horizontal axis represents the depth of the MOS image sensor from the surface of a cross-section taken along line B–B′ in FIG. 6B. In accordance with the depth, the MOS image sensor includes the gate electrode 16, the N-type layer 19 as the channel region, the carrier pocket region 20, the N-type well region 14, and the substrate 13. The vertical axis represents the potential in each of the regions of the MOS image sensor during operations in the imaging cycle. One imaging cycle includes a charge accumulation operation, a signal read operation and a reset operation.
As shown in FIG. 7, for the charge accumulation operation, the potential of the gate electrode 16 (gate voltage) is set to V0, and the charges (holes) are transferred from the light receiving diode 11 to the carrier pocket region 20 and accumulated. The concentration profile of each region is set such that the potential barrier ΔφINJ related to the transfer of the holes from the substrate 13 to the carrier pocket region 20 has a magnitude such that charges are not injected from the substrate 13 into the carrier pocket region 20.
Next, for the signal read operation, the potential of the gate electrode 16 is set to V1, and the potential of the drain voltage region 18 is set to VD. Thus, the potential of the N-type layer 19 as the channel region changes in accordance with the amount of the accumulated charges in the carrier pocket region 20. (For example, the potential of the N-type layer 19 becomes φ0 when the amount of the accumulated charges is 0, and the potential of the N-type layer 19 becomes φ1 when the amount of the accumulated charges is Qs). Such a change in the potential of the N-type layer 19 is read from the source region 17 as an output signal (hereinafter, referred to as an “S signal”) corresponding to the amount of the accumulated charges in the unit pixel section 10.
When the signal read operation is terminated, the potential of the gate electrode 16 is set to V2, which is high. This starts the reset operation of discharging the charges accumulated in the carrier pocket region 20 toward the substrate 13. After the reset operation, the potential of the gate electrode 16 is again set to V1, and a pixel reference signal (hereinafter, referred to as an “N signal”) is read from the source electrode 17 in a reset state. After the N signal is read, the operation of the MOS image sensor is returned to the charge accumulation operation (the potential of the gate electrode 16 is set to V0). Then, the next imaging cycle is performed. The imaging cycle is repeated in this manner.
FIGS. 8A and 8B are timing diagrams illustrating the gate voltage of each operation (charge accumulation operation, signal read operation, and reset operation) during the imaging cycle. FIG. 8A shows a change in the gate voltage of a selected row, and FIG. 8B shows a change in the gate voltage of an unselected row.
The gate voltage of a selected row changes as shown in FIG. 8A. During the charge accumulation operation, the gate voltage is V0. The gate voltage is changed to V1 in period T1, and the S signal is read.
In period T2, the gate voltage is changed to V2, which is high, and the reset operation is performed. In period T3, the gate voltage is returned to V1, and the N signal is read. Such a series of operations are performed in each imaging cycle.
In an unselected row (FIG. 8B), the gate voltage is V0, and charges are accumulated in the carrier pocket region 20.
The above-described threshold voltage modulation system MOS image sensor has a problem in that when a potential barrier ΔφRST related to the transfer of the charges (holes) from the carrier pocket region 20 to the substrate 13 exists during the reset operation, the charges partially remain in the carrier pocket region 20 (the amount of the remaining charges is represented by ΔQ).
FIG. 7 shows gate voltage V2 during the reset operation and gate voltage V2′ which is lower than V2. As represented by the comparison of these two voltages, the potential barrier ΔφRST and the remaining charge amount ΔQ rely on the gate voltage. A value of each of the potential barrier ΔφRST and the remaining charge amount ΔQ decreases as the gate voltage increases and approaches the high voltage V2.
When the remaining charge amount ΔQ increases due to the existence of the potential barrier ΔφRST increases the level of afterimage in an image. FIG. 9 shows the relationship between the remaining charge amount ΔQ and the level of afterimage.
As shown in FIG. 9, the remaining charge amount ΔQ in the carrier pocket region 20 is 0 when the gate voltage is V20 or higher. Therefore, the level of afterimage increases as the gate voltage decreases from V20, but no afterimage is generated when the gate voltage is V20 or higher.
It is experientially or experimentally known in the field of threshold voltage modulation type MOS image sensors that sensitivity variance (PRNU) among a plurality of unit pixel sections 10 increases when the remaining charge amount ΔQ decreases.
As shown in FIG. 9, when the gate voltage V2 during the reset operation becomes V21 (lower than V20 at or higher than which no afterimage is generated) or higher, the sensitivity variance (PRNU) rapidly increases.